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? 2009 microchip technology inc. ds80481a-page 1 PIC18F87J50 family the PIC18F87J50 family devices that you have received conform functionally to the current device data sheet (ds39775 b ), except for the anomalies described in this document. the silicon issues discussed in the following pages are for silicon revisions with the device and revision ids listed in table 1. the silicon issues are summarized in table 2. the errata described in this document will be addressed in future revisions of the PIC18F87J50 family silicon. data sheet clarifications and corrections start on page 5, following the discussion of silicon issues. the silicon revision level can be identified using the current version of mplab ? ide and microchip?s programmers, debuggers, and emulation tools, which are available at the microchip corporate web site (www.microchip.com). for example, to identify the silicon revision level using mplab ide in conjunction with mplab icd 2 or pickit? 3: 1. using the appropriate interface, connect the device to the mplab icd 2 programmer/ debugger or pickit? 3. 2. from the main menu in mplab ide, select c onfigure >s elect device , and then select the target part number in the dialog box. 3. select the mplab hardware tool ( debugger >s elect tool ). 4. perform a ?connect? operation to the device ( debugger >c onnect ). depending on the devel- opment tool used, the part number and device revision id value appear in the output window. the devrev values for the various PIC18F87J50 family silicon revisions are shown in table 1. note: this document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. only the issues indicated in the last column of table 2 apply to the current silicon revision ( a4 ). note: if you are unable to extract the silicon revision level, please contact your local microchip sales office for assistance. table 1: silicon devrev values part number device id (1) revision id for silicon revision (2) a2 a3 a4 pic18f65j50 410xh 2h 3h 3h pic18f66j50 414xh pic18f66j55 416xh pic18f67j50 418xh pic18f85j50 41axh pic18f86j50 41exh pic18f86j55 420xh PIC18F87J50 422xh note 1: the device ids (devid and devrev) are located at the last two implemented addresses of configuration memory space. they are shown in hexadecimal in the format ?devid devrev?. 2: refer to the ?pic18f6xjxx/8xjxx family flash microcontroller programming specification? (ds39644) for detailed information on device and revision ids for your specific device. PIC18F87J50 family silicon errata and data sheet clarification
PIC18F87J50 family ds80481a-page 2 ? 2009 microchip technology inc. table 2: silicon issue summary module feature item number issue summary affected revisions (1) a2 a3 a4 mssp i 2 c? slave 1. with i 2 c slave reception, need to read data promptly xxx mssp i 2 c master 2. with i 2 c master mode, narrow clock width upon slave clock stretch xxx eusart interrupts 3. if interrupts are enabled, 2 t cy delay needed after re-enabling the module xxx mssp spi master mode 4. spi master, write collision for f osc /64 and timer2/2 xxx porth rh0, rh1 5. in certain cases, pmp can override rh0 and rh1 xxx note 1: only those issues indicated in the last column apply to the current silicon revision.
? 2009 microchip technology inc. ds80481a-page 3 PIC18F87J50 family silicon errata issues 1. module: mssp (i 2 c? slave) when configured for i 2 c? slave reception, the mssp module may not receive the correct data, in extremely rare cases. this occurs only if the serial receive/transmit buffer register (sspbuf) is not read after the sspif interrupt (pir1<3>) has occurred, but before the first rising clock edge of the next byte being received. work around the issue can be resolved in either of these ways: ? prior to the i 2 c slave reception, enable the clock stretching feature. this is done by setting the sen bit (sspcon2<0>). ? each time the sspif is set, read the sspbuf before the first rising clock edge of the next byte being received. affected silicon revisions 2. module: mssp (i 2 c? master) when in i 2 c master mode, if the slave performs clock stretching, the first clock pulse after the slave releases the scl line may be narrower than the configured clock width. this may result in the slave missing the first clock in the next transmission/ reception. work around the clock pulse will be the normal width if the slave does not perform clock stretching. affected silicon revisions 3. module: enhanced universal synchronous asynchronous receiver transmitter (eusart) in rare situations, when interrupts are enabled, unexpected results may occur if: ? the eusart is disabled (spen bit (rcstax<7>) = 0 ) ? the eusart is re-enabled (rcstax<7> = 1 ) ? a two-cycle instruction is executed immediately after enabling the module (setting spen, cren or txen = 1 ) work around add a 2 t cy delay after any instruction that re- enables the eusart module (ex: sets spen = 1 ). see example 1. example 1: re-enabling a eusart module affected silicon revisions note: this document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. only the issues indicated by the shaded column in the following tables apply to the current silicon revision ( a4 ). a2 a3 a4 xx x a2 a3 a4 xx x ;initial conditions: spen = 0 (module disabled) ;to re-enable the module: ;re-initialize txstax, baudconx, spbrgx, spbrghx registers (if needed) ;re-initialize rcstax register (if needed), but do not set spen = 1 yet ;now enable the module, but add a 2-tcy delay before executing any two-cycle ;instructions bsf rcsta1, spen ;or rcsta2 if eusart2 nop ;1 tcy delay nop ;1 tcy delay (two total) ;cpu may now execute 2 cycle instructions a2 a3 a4 xx x
PIC18F87J50 family ds80481a-page 4 ? 2009 microchip technology inc. 4. module: mssp with mssp1 or mssp2 in spi master mode, the f osc /64 or timer2/2 clock rate enabled and cke = 0 , a write collision may occur if sspbuf is loaded immediately after the transfer is complete. a delay may be required before writing sspbuf, after the mssp interrupt flag bit (sspif) is set or the buffer full bit (bf) is set. if the delay is insufficiently short, a write collision may occur as indicated by the wcol bit being set. work around add a software delay of one sck period after detecting the completed transfer and prior to updating the sspbuf contents. affected silicon revisions 5. module: i/o (porth) when the parallel master port (pmp) module is enabled (pmconh<7> = 1 ) and the pmpmx bit is clear (config3l<2> = 0 ), the pmp module can, under certain conditions, override firmware control over the rh0 and rh1 general purpose i/o (gpio) pins. the rh0 and rh1 pins will function normally and can still be used as standard gpio if the pmp is disabled or the pmpmx configuration bit is set. this issue only applies to the 80-pin devices (pic18f85j50, pic18f86j50, pic18f86j55 and PIC18F87J50). work around none. affected silicon revisions a2 a3 a4 xx x a2 a3 a4 xx x
? 2009 microchip technology inc. ds80481a-page 5 PIC18F87J50 family data sheet clarifications the following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (ds39775 b ): 1. module: table 28-1: memory programming requirements on page 430, parameter d132b is renamed, and the minimum and maximum voltage levels and conditions column of the self-timed erase or write for v dd and v ddcore for are included. the t we parameter number and conditions column are changed. the changed content is indicated in bold text in table 28-1: table 28-1: memory programming requirements note: corrections are shown in bold . where possible, the original bold text formatting has been removed for clarity. dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. sym characteristic min typ? max units conditions program flash memory d130 e p cell endurance 10k ? ? e/w -40 c to +85 c d131 v pr v ddcore for read v min ?3.6vv min = minimum operating voltage d132 v pew voltage for self-timed erase or write v dd v ddcore 2.35 2.25 ? ? 3.6 2.7 v v envreg tied to v dd envreg tied to v ss d133a t iw self-timed write cycle time ? 2.8 ? ms d133b t ie self-timed page erase cycle time ?33.0?ms d134 t retd characteristic retention 20 ? ? year provided no other specifications are violated d135 i ddp supply current during programming ?10?ma d140 t we writes per erase cycle ? ? 1 ? for each physical address ? data in ?typ? column is at 3.3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested.
PIC18F87J50 family ds80481a-page 6 ? 2009 microchip technology inc. 2. module: table 28-2: comparator specifications on page 431, the maximum input offset voltage (parameter d300) is changed to 25 mv. the parameter numbers for t resp and t mc 2 ov are changed to d303 and d304, respectively. a new parameter number, d305, for v irv is added. the changed/appended content is indicated in bold text in table 28-2. 3. module: table 28-4: internal voltage regulator specifications on page 431, additional comments are provided to help guide selection of an external capacitor. the changed/appended content is indicated in bold text in table 28-4. table 28-2: comparator specifications table 28-4: internal voltag e regulator specifications operating conditions: 3.0v < v dd < 3.6v, -40c < t a < +85c (unless otherwise stated) param no. sym characteristics min typ max units comments d300 v ioff input offset voltage ? 5.0 25 mv d301 v icm input common mode voltage 0 ? av dd ? 1.5 v d302 cmrr common mode rejection ratio 55 ? ? db d303 t resp response time (1) ? 150 400 ns d304 t mc 2 ov comparator mode change to output valid ?? 10 s d305 v irv internal reference voltage ? 1.2 ? v note 1: response time measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions from v ss to v dd . operating conditions: -40c < t a < +85c (unless otherwise stated) param no. sym characteristics min typ max units comments v rgout regulator output voltage 2.45 2.5 ? v v dd , envreg = 3.0v c efc external filter capacitor value (1) 4.7 (2) 10 ? f capacitor must be low series resistance (<5 ) note 1: c efc applies when the internal regulator is enabled (envreg = v dd ). when the regulator is disabled (envreg = v ss ), there is no minimum or maximum capacitance, but good supply rail bypassing should still be practiced. 2: if the regulator is enabled and the v dd supply rail has moderate ripple voltage, it is recommended that more than the minimum c efc be used.
? 2009 microchip technology inc. ds80481a-page 7 PIC18F87J50 family 4. module: section 28.3 ?dc characteristics: PIC18F87J50 family (industrial)? on page 428, the characteristics and conditions of the input leakage current are updated for the analog (d060) and included for the digital (d060a) i/o ports. the changed content is indicated in bold text in the ?dc characteristics? table. dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min max units conditions v il input low voltage all i/o ports: d030 with ttl buffer v ss 0.15 v dd vv dd < 3.3v d030a ? 0.8 v 3.3v v dd 3.6v d031 with schmitt trigger buffer v ss 0.2 v dd v d032 mclr v ss 0.2 v dd v d033 osc1 v ss 0.3 v dd v hs, hspll modes d033a d034 osc1 t1cki v ss v ss 0.2 v dd 0.3 v v ec, ecpll modes v ih input high voltage i/o ports with non 5.5v tolerance: (2) d040 with ttl buffer 0.25 v dd + 0.8v v dd vv dd < 3.3v d040a 2.0 v dd v3.3v v dd 3.6v d041 with schmitt trigger buffer 0.8 v dd v dd v i/o ports with 5.5v tolerance: (2) dxxx with ttl buffer 0.25 v dd + 0.8v 5.5 v v dd < 3.3v dxxxa 2.0 5.5 v 3.3v v dd 3.6v dxxx with schmitt trigger buffer 0.8 v dd 5.5 v d042 mclr 0.8 v dd v dd v d043 osc1 0.7 v dd v dd v hs, hspll modes d043a d044 osc1 t1cki 0.8 v dd 1.6 v dd v dd v v ec, ecpll modes i il input leakage current (1) d060 i/o ports with non 5.5v tolerance: (2) ? 1 av ss v pin v dd , pin at high-impedance d060a i/o ports with 5.5v tolerance: (2) ? 1 av ss v pin 5.5v, pin at high-impedance d061 mclr ? 1 avss v pin v dd d063 osc1 ? 5 avss v pin v dd note 1: negative current is defined as current sourced by the pin. 2: refer to table 10-1 for the pins that have corresponding tolerance limits.
PIC18F87J50 family ds80481a-page 8 ? 2009 microchip technology inc. 5. module: section 19.3 ?spi mode? and section 19.4 ?i 2 c? mode? in section 19.3 ?spi mode? on page 231 and section 19.4 ?i 2 c? mode? on page 241, the following note is added to describe the procedure to disable the mssp module: 6. module: figure 19-10: i 2 c? slave mode timing (transmission, 7-bit address) on page 252, the figure is replaced with the new timing diagram provided in figure 19-10. note: disabling the mssp module by clearing the sspen bit (sspxcon1<5>) may not reset the module. it is recommended to clear the sspxstat, sspxcon1 and sspxcon2 registers and select the mode prior to setting the sspen bit to enable the mssp module.
? 2009 microchip technology inc. ds80481a-page 9 PIC18F87J50 family figure 19-10: i 2 c? slave mode timing (transmission, 7-bit address) sdax sclx bf (sspxstat<0>) a6 a5 a4 a3 a2 a1 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 sspxbuf is written in software cleared in software data in sampled s ack transmitting data r/w = 0 ack receiving address a7 d7 9 1 d6 d5 d4 d3 d2 d1 d0 2 3 4 5 6 7 8 9 sspxbuf is written in software cleared in software from sspxif isr transmitting data d7 1 ckp (sspxcon<4>) p ack ckp is set in software ckp is set in software sclx held low while cpu responds to sspxif sspxif (pir1<3> or pir3<7>) from sspxif isr clear by reading
PIC18F87J50 family ds80481a-page 10 ? 2009 microchip technology inc. 7. module: figure 19-24: i 2 c? master mode waveform (reception, 7-bit address) on page 269, the condition, r/w , when the acknowl- edge signal (ack) is received from the slave, after transmitting the address to the slave, is changed to ? 1 ?. the changed value is indicated in bold text in figure 19-24.
? 2009 microchip technology inc. ds80481a-page 11 PIC18F87J50 family figure 19-24: i 2 c? master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 123456 789 12345678 9 123 4 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 1 transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1 ), write to sspbuf occurs here, ack from slave master configured as a receiver by programming sspcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sda = 0 , scl = 1 while cpu ack cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif ack from master, set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknowledge sequence of receive set acken, start acknowledge sequence, sda = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspcon2<4> to start acknowledge sequence, sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically acken begin start condition cleared in software sda = ackdt = 0 last bit is shifted into sspsr and contents are unloaded into sspbuf cleared in software sspov is set because sspbuf is still full responds to sspif
PIC18F87J50 family ds80481a-page 12 ? 2009 microchip technology inc. 8. module: mssp (spi master) in section 19.3.6, ?master mode,? the following content is added: when used in timer2 output/2 mode, the spi bit rate can be configured using the pr2 period register and the timer2 prescaler. to operate in this mode, firmware must first initialize and enable the timer2 module before it can be used with the mssp. once enabled, the timer2 module is free running and mostly independent of the mssp module. writing to the sspxbuf register will not clear the current tmr2 value in hardware. this can result in an unpredictable spi transmit msb bit width, depending on how close the tmr2 regis- ter was to the pr2 match condition at the moment that the firmware wrote to sspxbuf. to avoid the unpredictable msb bit width, initial- ize the tmr2 register to a known value when writing to sspxbuf. an example procedure, which provides predictable bit widths (only needed in the timer2/2 mode), is given in example 2. the example procedure demon- strates operation with mssp1, but the concepts apply equally to mssp2. example 2: loading sspxbuf with the timer2/2 clock mode 9. module: osctune register the second paragraph of section 2.2.5.1 ?osctune register? is modified as indicated: when the osctune register is modified, the intosc frequency begins shifting to the new value. the intosc clock stabilizes within 1 ms. code execution continues during this shift. there is no indication that the shift has occurred. transmitspi: bcf pir1, ssp1if ;make sure interrupt flag is clear (may have been set from previous ;transmission) movf ssp1buf, w ;perform read, even if the data in sspbuf is not important movwf rxdata ;save previously received byte in user ram, if the data is meaningful bcf t2con, tmr2on ;turn off timer when loading sspbuf clrf tmr2 ;set timer to a known state movf txdata, w ;wreg = contents of txdata (user data to send) movwf ssp1buf ;load data to send into transmit buffer bsf t2con, tmr2on ;start timer to begin transmission waitcomplete: ;loop until data has finished transmitting btfss pir1, ssp1if ;interrupt flag set when transmit is complete bra waitcomplete
? 2009 microchip technology inc. ds80481a-page 13 PIC18F87J50 family appendix a: document revision history rev a document (9/2009) initial release of the combined, silicon errata/data sheet clarification document. new silicon issues 4 (mssp) and 5 (i/o ? porth). new data sheet clarifications 8 (mssp ? spi master) and 9 (osctune register). this document replaces these errata documents: ? ds80321b, ?PIC18F87J50 family rev. a2 silicon errata? ? ds80415a, ?PIC18F87J50 family rev. a3 silicon errata? ? ds80409b, ?PIC18F87J50 family data sheet errata?
PIC18F87J50 family ds80481a-page 14 ? 2009 microchip technology inc. notes:
? 2009 microchip technology inc. ds80481a-page 15 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, octopus, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, pic 32 logo, real ice, rflab, select mode, total endurance, tsharc, uniwindr iver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2009, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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